The FPGA SDRAM data path is actually 32 bits (2x16) so that helps, but its going to be a bitch to get it working. The example code uses a Nios II soft-core processor, and from what I've seen of the equivalent DE0-Nano code, its going to be messy to bolt the SDRAM controller onto a mining core, especially as we'll need to use burst mode for speed. So, my goal is to print (on the standard output) a number using a Nios II system on a FPGA Cyclone II Altera. MY STEPS: 1) I created the following Nios II system with the Qsys tool (Quartus II): (NIOS II CPU - JTAG - ONCHIP MEMORY RAM - SYS ID) 2) I wrote the following C code: Intel Altera FPGA Families • High & Medium Density FPGAs Stratix™II, Stratix, APEX™II, APEX 20K, & FLEX® 10K • Low-Cost FPGAs Cyclone™& ACEX® 1K • FPGAs with Clock Data Recovery Stratix GX & Mercury™ • CPLDs MAX® 7000 & MAX 3000 • Embedded Processor Solutions Nios ™, Excalibur • Configuration Devices EPC 15 16 Cyclone IV E Cyclone IV GX Cyclone V E Cyclone V GT Cyclone V GX Cyclone V SE while FPGA examples include Bitcoin mining or OpenCL-based accelerators. The FPGA A number of CPU cores (such as NIOS-II/Microblaze or custom processors) are located on each FPGA. Each FPGA board has up to 16GB of DRAM. When a CPU core needs ALTERA Cyclone II EP2C5T144 FPGA Development Board Kits EPROM EPCS4. £15.85. From China (£15.85/Unit) Brand: Unbranded. Free postage. or Best Offer. USB Blaster Altera Debugger Cpld Fpga Nios Jtag. £14.99. From Germany. £6.34 postage. Brand: Unbranded. See similar items. ALTERA FPGA Cyslonell EP2C5T144 Minimum System Learning Board
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Made with Altera Cyclone II FPGA on DE2 board. The S-DSP part is a full hardware Avalon component. The S-SMP part (SPC700) is SNES9X ported to Nios II. SPC files are stored in a Flash ROM. Speech Recognition using Altera Cyclone II FPGA designed using NIOS 2 and verilog - Duration: 4:35. Kaustubh Pande 2,283 views. 4:35. Language: English Location: United States A learning tutorial for Beginners to display "Hello World" on NIOS II console. ... Altera FPGA tutorial - FIR filter on Altera FPGA as Hardware Accelerator (DE1 Board) - Duration: 23:03. Altera FPGA Cyclone NIOS II EP2C8Q208 Development Board.